To make a high current, high voltage, low on-resistance, vertical SiC power MOSFET has, so far, been impractical, at least in part, due to the poor surface mobility of electrons in the inversion layer. Recently, some processing techniques have been developed on a lateral MOSFET structure, which result in an improved surface electron mobility. However, a power MOSFET structure may involve additional processing including, for example, anneals at temperatures of greater than 1500° C. for the activation of p-type dopants, for example, p-well/p+ contact/p− Junction Termination Extension (JTE) implants. Such anneals may have detrimental impact on the performance of power MOSFETs fabricated using such techniques.
A number of silicon carbide power MOSFET structures have been described in the literature. See e.g. U.S. Pat. No. 5,506,421; A. K. Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek, M. H. White, and C. D. Brandt, “1.1 kV 4H-SiC Power UMOSFET's,” IEEE Electron Device Letters, Vol. 18, No. 12, pp. 586-588, December 1997; A. K. Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek and C. D. Brandt, “1400 V 4H-SiC Power MOSFETs,” Materials Science Forum Vols. 264-268, pp. 989-992, 1998; J. Tan, J. A. Cooper, Jr., and M. R. Melloch, “High-Voltage Accumulation-Layer UMOSFETs in 4H-SiC,” IEEE Electron Device Letters, Vol. 19, No. 12, pp. 487-489, December 1998; J. N. Shenoy, J. A. Cooper and M. R. Melloch, “High-Voltage Double-Implanted Power MOSFET's in 6H-SiC,” IEEE Electron Device Letters, Vol. 18, No. 3, pp. 93-95, March 1997; J. B. Casady, A. K. Agarwal, L. B. Rowland, W. F. Valek, and C. D. Brandt, “900 V DMOS and 1100 V UMOS 4H-SiC Power FETs,” IEEE Device Research Conference, Ft. Collins, Colo., Jun. 23-25, 1997; R. Schomer, P Friedrichs, D. Peters, H. Mitlehner, B. Weis and D. Stephani, “Rugged Power MOSFETs in 6H-SiC with Blocking Capability up to 1800 V,” Materials Science Forum Vols. 338-342, pp. 1295-1298, 2000; V. R. Vathulya and M. H. White, “Characterization of Channel Mobility on Implanted SiC to determine Polytype suitability for the Power DIMOS structure,” Electronic Materials Conference, Santa Barbara, Calif., Jun. 30-Jul. 2, 1999; A. V. Suvorov, L. A. Lipkin, G. M. Johnson, R. Singh and J. W. Palmour, “4H-SiC Self-Aligned Implant-Diffused Structure for Power DMOSFETs,” Materials Science Forum Vols. 338-342, pp. 1275-1278, 2000; P. M. Shenoy and B. J. Baliga, “The Planar 6H-SiC ACCUFET: A New High-Voltage Power MOSFET Structure,” IEEE Electron Device Letters, Vol. 18, No. 12, pp. 589-591, December 1997; Ranbir Singh, Sei-Hyung Ryu and John W. Palmour, “High Temperature, High Current, 4H-SiC Accu-DMOSFET,” Materials Science Forum Vols. 338-342, pp. 1271-1274, 2000; Y. Wang, C. Weitzel and M. Bhatnagar, “Accumulation-Mode SiC Power MOSFET Design Issues,” Materials Science Forum Vols. 338-342, pp. 1287-1290, 2000; and A. K. Agarwal, N. S. Saks, S. S, Mani, V. S. Hegde and P. A. Sanger, “Investigation of Lateral RESURF, 6H-SiC MOSFETs,” Materials Science Forum Vols. 338-342, pp. 1307-1310, 2000.
The existing SiC structures can, generally, be divided into three categories: (1) Trench or UMOSFET, (2) Vertical Doubly Implanted MOSFET (DIMOSFET), and (3) Lateral Diffused MOSFET (LDMOSFET). Of these structures, the vertical DIMOSFET structure, illustrated in FIG. 1, is a variation of the diffused (DMOSFET) structure employed in silicon technology. Typically, the p-wells are implanted with Al or Boron, the source regions (n+) are implanted with nitrogen or phosphorus, and the p+ regions are usually implanted with Al. The implants are activated at temperatures between 1400° C.-1700° C. The contacts to n+ layers are made with nickel (Ni) and annealed and the contacts to p+ are made by Ni, Ti or Ti/Al. Both contacts are annealed at high temperatures, The gate dielectric is, typically, either thermally grown (Thermal SiO2) or deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and subsequently annealed in various ambients. The deposited dielectric may, for example, be SiO2 or an Oxide/Nitride/Oxide (ONO) stack.
The interface states near the conduction band edge tend to trap the otherwise free electrons from the inversion layer leaving a relatively small number of free electrons in the inversion layer. Also the trapped electrons may create negatively charged states at the interface which coulomb scatter the free electrons. The reduced number of free electrons and the increased scattering may reduce the conduction of current from source to drain, which may result in low effective mobility of electrons and a high on-resistance. Several factors have been attributed to the high density of states near the conduction band edge: (1) carbon or silicon dangling bonds, (2) carbon clusters, and (3) Si—Si bonds creating a thin amorphous silicon layer at the interface. See S. T. Pantelides, “Atomic Scale Engineering of SiC Dielectric Interfaces,” DARPA/MTO High Power and ONR Power Switching MURI Reviews, Rosslyn, Va., Aug. 10-12, 1999 and V. V. Afanas'ev, M, Bassler, G. Pensl, and M. Schulz, “Intrinsic SiC/SiO2 Interface States,” Phys. Stat. Sol. (a), Vol. 162, pp. 321-337, 1997.
In addition to the high density of interface states, several other mechanisms have also been attributed to the poor mobility of inversion layer electrons: (1) Al segregating out of the Al-doped, p-type SiC, and (2) Surface roughness created by the high temperature activation of implanted impurities. See S. Sridevan, P. K, McLarty, and B. J. Baliga, “On the Presence of Aluminum in Thermally Grown Oxides on 6H-Silicon Carbide,” IEEE Electron Device Letters, Vol. 17, No. 3, pp. 136-138, March 1996 and M. A. Capano, S. Ryu, J. A. Cooper, Jr., M. R. Melloch, K. Rottner, S. Karlsson, N. Nordell, A. Powell, and D. E. Walker, Jr., “Surface Roughening in Ion Implanted 4H-Silicon Carbide,” Journal of Electronic Materials, Vol. 28, No. 3, pp. 214-218, March, 1999. Researchers from Purdue University have concluded that a direct correlation exists between the inversion layer electron mobility and the implant activation temperature. Such research has concluded that lower implant activation temperature (1200° C.) leads to higher electron mobility and higher activation temperature (1400° C.) results in poor electron mobility. See M. K. Das, J. A. Cooper, Jr., M. R. Melloch, and M. A. Capano, “Inversion Channel Mobility in 4H- and 6H-SiC MOSFETs,” IEEE Semiconductor Interface Specialists Conference, San Diego, Calif., Dec. 3-5, 1998. These results have been obtained on planar MOSFETs, which do not utilize an implantation of the p-well. The p-well implanted impurity (Al or Boron) typically requires at least a 1500° C. activation temperature.
A further difficulty with DIMOSFETS may be associated with the “JFET” region of the device. As seen in FIG. 1, a depletion region may be formed in the n− drift region around the p-well. This depletion region may effectively make the channel length longer than the p-well junction depth as current flow is provided around the depletion region. It has been suggested that a spacer implant be introduced between the p-well regions to alleviate this problem. See Vathulya et al., “A Novel 6H-SiC DMOSFET With Implanted P-Well Spacer”, IEEE Electron Device Letters, Vol. 20, No. 7, p. 354, July 1999. This spacer implant does not extend past the p-well regions and does not significantly reduce the JFET resistance if the depletion region formed at the p-well and then drift region interface extends deep into the n drift region.